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| IRF9140 Data Sheet February 1999 File Number 2278.3 -19A, -100V, 0.200 Ohm, P-Channel Power MOSFET These are P-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17521. Features * -19A, -100V * rDS(ON) = 0.200 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRF9140 PACKAGE TO-204AA BRAND IRF9140 Symbol D NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-204AA DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 5-14 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF9140 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF9140 -100 -100 -19 -12 -76 20 125 1 960 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (See Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured Between the Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die Measured From The Source Lead, 6mm (0.25in) From the Flange and the Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S TEST CONDITIONS VGS = 0V, ID = -250A (Figure 10) VGS = VDS, ID = -250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC VDS > ID(ON) x rDS(ON) Max, VGS = -10V (Figure 7) VGS = 20V VGS = -10V, ID = -10A (Figures 8, 9) VDS > ID(ON) x rDS(ON) Max, ID = -10A VDD = -50V, ID -19A, RG = 9.1, RL = 2.3 (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature MIN -100 -2.0 -19 5.0 - TYP 0.15 7.0 16 65 47 28 70 14 56 1100 550 250 5.0 MAX -4.0 -25 -250 100 0.20 20 100 70 90 90 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance VGS = -10V, ID = -19A, VDS = 0.8 x Rated BVDSS, Ig (REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = -25V, f = 1.0MHz (Figure 10) - Internal Source Inductance LS - 12.5 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA Free Air Operation - - 1 30 oC/W oC/W 5-15 IRF9140 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX -19 -76 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES: VSD trr QRR TJ = 25oC, ISD = -19A, VGS = 0V TJ = 150oC, ISD = 19A, dISD/dt = 100A/s TJ = 150oC, ISD = -19A, dISD/dt = 100A/s - 170 0.8 -1.5 - V ns C 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 4H, RG = 25, peak IAS = 19A. See Figures 15, 16. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 Unless Otherwise Specified -20 ID, DRAIN CURRENT (A) -15 0.8 0.6 0.4 -10 -5 0.2 0.0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 0 0 50 100 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 ZJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE PDM t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-4 10-3 10-2 0.1 1 10 0.01 10-5 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 5-16 IRF9140 Typical Performance Curves 102 10s 100s 10 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 1 TJ = MAX RATED TC = 25oC RJC = 1oC/W SINGLE PULSE 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 1ms 10ms 100ms DC Unless Otherwise Specified (Continued) -100 VGS = -16V -80 VGS = -12V -60 VGS = -10V -40 VGS = -9V VGS = -8V -20 VGS = -7V VGS = -6V VGS = -5V VGS = -14V 80s PULSE TEST ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 0 0 VGS = -4V -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) -50 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS -50 80s PULSE TEST VGS = -16V VGS = -14V VGS = -12V VGS = -10V VGS = -9V ID, DRAIN CURRENT (A) -102 -5 -2 -10 -5 -2 -1.0 -5 -2 -0.1 0 -2 -12 -4 -6 -8 -10 VGS, GATE TO SOURCE VOLTAGE (V) -14 TJ = 125oC TJ = 25oC TJ = -55oC 80s PULSE TEST ID, DRAIN CURRENT (A) -40 -30 VGS = -8V -20 VGS = -7V VGS = -6V VGS = -5V 0 0 VGS = -4V -2 -4 -6 -8 -10 VDS, DRAIN TO SOURCE VOLTAGE (V) -10 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 0.26 80s PULSE TEST NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE 0.22 VGS = -10V 2.5 ID = -10A VGS = -10V 2.0 0.18 1.5 0.14 VGS = -20V 1.0 0.10 0.5 0 0 -20 -40 -60 ID, DRAIN CURRENT (A) -80 -100 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 5-17 IRF9140 Typical Performance Curves 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE Unless Otherwise Specified (Continued) 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS 1.15 C, CAPACITANCE (pF) 1600 1.05 1200 0.95 800 COSS CRSS 0.85 400 0.75 -60 -40 -20 0 20 40 60 80 100 120 140 160 0 0 -10 -20 -30 -40 -50 TJ, JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 15 IDR, SOURCE TO DRAIN CURRENT (A) 80s PULSE TEST gfs, TRANSCONDUCTANCE (S) 12 TJ = -55oC TJ = 25oC 9 TJ = 125oC 102 5 2 10 5 2 1.0 5 2 0.1 0.4 TJ = 150oC TJ = 25oC 6 3 0 0 -20 -40 -60 ID, DRAIN CURRENT (A) -80 -100 0.6 0.8 1.0 1.2 1.4 1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) 1.8 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 VGS, GATE TO SOURCE VOLTAGE (V) ID = -24A -5 VDS = -20V VDS = -50V -10 VDS = -80V -15 -20 0 20 40 60 Qg(TOT), TOTAL GATE CHARGE (nC) 80 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5-18 IRF9140 Test Circuits and Waveforms VDS tAV 0 VARY tP TO OBTAIN REQUIRED PEAK IAS RG L + VDD 0V VGS DUT tP IAS 0.01 VDD IAS tP BVDSS VDS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL 0 10% tOFF td(OFF) tf 10% DUT VGS RG VDD + VDS VGS 0 90% 90% 10% 50% PULSE WIDTH 90% 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR 0 VDS DUT 12V BATTERY 0.2F 50k 0.3F Qgs D G 0 Ig(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR DUT Qgd Qg(TOT) VDD 0 VGS IG(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 5-19 IRF9140 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 5-20 |
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